Low Power, Buffered 24-Bit
FEATURES FUNCTIONAL BLOCK DIAGRAM
Power GND VDD REFIN(+) REFIN(�)
Supply: 2.5 V to 5.25 V operation
Normal: 75 �A max VDD CLOCK
Power-down: 1 �A max
AIN(+) BUF - DOUT/RDY
RMS noise: 1.1 �V at 9.5 Hz update rate AIN(�) ADC DIN
19.5-bit p-p resolution (22 bits effective resolution) SERIAL SCLK
Integral nonlinearity: 3.5 ppm typical GND INTERFACE CS
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator AD7791
Rail-to-rail input buffer
VDD monitor channel 04227-0-001
Temperature range: �40�C to +105�C
10-lead MSOP Figure 1.
INTERFACE GENERAL DESCRIPTION
3-wire serial The AD7791 is a low power, complete analog front end for
SPI�, QSPITM, MICROWIRETM, and DSP compatible low frequency measurement applications. It contains a low
Schmitt trigger on SCLK noise 24-bit - ADC with one differential input that can be
buffered or unbuffered.
The device operates from an internal clock. Therefore, the user
Smart transmitters does not have to supply a clock source to the device. The output
Battery applications data rate from the part is software programmable and can be
Portable instrumentation varied from 9.5 Hz to 120 Hz, with the rms noise equal to
Sensor measurement 1.1 �V at the lower update rate. The internal clock frequency
Temperature measurement can be divided by a factor of 2, 4, or 8, which leads to a reduc-
Pressure measurement tion in the current consumption. The update rate, cutoff
Weigh scales frequency, and settling time will scale with the clock frequency.
4 to 20 mA loops
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 �W maximum. It is housed in a 10-lead MSOP.
Rev. 0 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use. Fax: 781.326.8703 � 2003 Analog Devices, Inc. All rights reserved.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
AD7791 ADC Circuit Information.............................................................. 14
Overview ..................................................................................... 14
TABLE OF CONTENTS Noise Performance ..................................................................... 14
Reduced Current Modes ........................................................... 14
AD7791--Specifications.................................................................. 3 Digital Interface .......................................................................... 15
Timing Characteristics..................................................................... 5 Single Conversion Mode ....................................................... 16
Absolute Maximum Ratings............................................................ 7 Continuous Conversion Mode............................................. 16
Pin Configuration and Function Descriptions............................. 8 Continuous Read Mode ........................................................ 17
Typical Performance Characteristics ............................................. 9
On-Chip Registers .......................................................................... 10 Circuit Description......................................................................... 18
Analog Input Channel ............................................................... 18
Communications Register Bipolar/Unipolar Configuration .............................................. 18
(RS1, RS0 = 0, 0) ......................................................................... 10 Data Output Coding .................................................................. 18
Status Register Reference Input........................................................................... 18
(RS1, RS0 = 0, 0; Power-on/Reset = 0x8C).............................. 11 VDD Monitor ................................................................................ 19
Mode Register Grounding and Layout .............................................................. 19
(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 11
Filter Register Outline Dimensions ....................................................................... 20
(RS1, RS0 = 1, 0; Power-on/Reset = 0x04)............................... 12
(RS1, RS0 = 1, 1; Power-on/Reset = 0x000000) ...................... 13
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(�) = GND; GND = 0 V; CDIV1 = CDIV0 = 0;
all specifications TMIN to TMAX, unless otherwise noted.)
Parameter AD7791B Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate 9.5 Hz min nom
120 Hz max nom
No Missing Codes2 24 Bits min Update Rate 20 Hz
Resolution 19.5 Bits p-p 9.5 Hz Update Rate
Output Noise 1.1 �V rms typ
Integral Nonlinearity �15 ppm of FSR max 3.5 ppm typ
Offset Error �3 �V typ
Offset Error Drift vs. Temperature �10 nV/�C typ
Full-Scale Error3 �10 �V typ
Gain Drift vs. Temperature �0.5 ppm/�C typ
Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V
Differential Input Voltage Ranges �REFIN V nom REFIN = REFIN(+) � REFIN(�);
Absolute AIN Voltage Limits2 GND + 100 mV V min Buffered Mode of Operation
VDD � 100 mV V max
Analog Input Current Buffered Mode of Operation
Average Input Current2 �1 nA max
Average Input Current Drift �5 pA/�C typ
Absolute AIN Voltage Limits2 GND � 30 mV V min Unbuffered Mode of Operation
VDD + 30 mV V max
Analog Input Current Unbuffered Mode of Operation
Input current varies with input voltage.
Average Input Current �400 nA/V typ
Average Input Current Drift �50 pA/V/�C typ
Normal Mode Rejection2
@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 � 1 Hz, 60 � 1 Hz, FS[2:0] = 1004
@ 50 Hz 80 dB min 90 dB typ, 50 � 1 Hz, FS[2:0] = 1014
@ 60 Hz 80 dB min 90 dB typ, 60 � 1 Hz, FS[2:0] = 0114
Common Mode Rejection AIN = 1 V
@DC 90 dB min 100 dB typ, FS[2:0] = 1004
@ 50 Hz, 60 Hz2 100 dB min 50 � 1 Hz (FS[2:0] = 1014), 60 � 1 Hz (FS[2:0] = 0114)
REFIN Voltage 2.5 V nom REFIN = REFIN(+) � REFIN(�)
Reference Voltage Range2 0.1 V min
Absolute REFIN Voltage Limits2 V DD V max
GND � 30 mV V min
VDD + 30 mV V max
Average Reference Input Current 0.5 �A/V typ
Average Reference Input Current Drift �0.03 nA/V/�C typ
1 Temperature Range �40�C to +105�C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (VDD = 4 V).
4 FS[2:0] are the three bits used in the filter register to select the output word rate.
Rev. 0 | Page 3 of 20
Parameter AD7791B Unit Test Conditions/Comments
REFERENCE INPUT (continued)
Normal Mode Rejection2 65 dB min 73 dB typ, 50 � 1 Hz, 60 � 1 Hz, FS[2:0] = 1004
@ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 � 1 Hz, FS[2:0] = 1014
@ 50 Hz 80 dB min 90 dB typ, 60 � 1 Hz, FS[2:0] = 0114
@ 60 Hz AIN = 1 V
Common Mode Rejection 100 dB typ FS[2:0] = 1004
@ DC 110 dB typ 50 � 1 Hz (FS[2:0] = 1014), 60 � 1 Hz (FS[2:0] = 0114)
@ 50 Hz, 60 Hz
0.8 V max VDD = 5 V
LOGIC INPUTS 0.4 V max VDD = 3 V
All Inputs Except SCLK2 2.0 V min VDD = 3 V or 5 V
VINL, Input Low Voltage
1.4/2 V min/V max VDD = 5 V
VINH, Input High Voltage 0.8/1.4 V min/V max VDD = 5 V
SCLK Only (Schmitt-Triggered Input)2 0.3/0.85 V min/V max VDD = 5 V
VT(+) 0.9/2 V min/V max VDD = 3 V
VT(�) 0.4/1.1 V min/V max VDD = 3 V
VT(+) � VT(�) 0.3/0.85 V min/V max VDD = 3 V
VT(+) �1 �A max VIN = VDD or GND
VT(�) 10 pF typ All Digital Inputs
VT(+) - VT(�)
Input Currents VDD � 0.6 V min VDD = 3 V, ISOURCE = 100 �A
Input Capacitance 0.4 V max VDD = 3 V, ISINK = 100 �A
LOGIC OUTPUTS 4 V min VDD = 5 V, ISOURCE = 200 �A
VOH, Output High Voltage2 0.4 V max VDD = 5 V, ISINK = 1.6 mA
VOL, Output Low Voltage2 �1 �A max
VOH, Output High Voltage2 10 pF typ 65 �A typ, VDD = 3.6 V, Unbuffered Mode
VOL, Output Low Voltage2 Offset Binary 130 �A typ, VDD = 3.6 V, Buffered Mode
Floating-State Leakage Current V min/max 73 �A typ, VDD = 5.25 V, Unbuffered Mode
Floating-State Output Capacitance 2.5/5.25 145 �A typ, VDD = 5.25 V, Buffered Mode
Data Output Coding �A max
POWER REQUIREMENTS5 75 �A max
Power Supply Voltage 145 �A max
VDD � GND 80 �A max
Power Supply Currents 160 �A max
IDD Current6 1
IDD (Power-Down Mode)
5 Digital inputs equal to VDD or GND.
6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).
Rev. 0 | Page 4 of 20
TIMING CHARACTERISTICS1, 2
Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(�) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = VDD, unless otherwise noted.)
Parameter Limit at TMIN, TMAX Unit Conditions/Comments
t3 100 ns min SCLK High Pulsewidth
t4 100 ns min SCLK Low Pulsewidth
t1 0 ns min CS Falling Edge to DOUT/RDY Active Time
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.5 V to 3.6 V
ns min SCLK Active Edge to Data Valid Delay4
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.5 V to 3.6 V
ns min Bus Relinquish Time after CS Inactive Edge
t55, 6 10
80 ns max
t6 100 ns max SCLK Inactive Edge to CS Inactive Edge
t7 10 ns min SCLK Inactive Edge to DOUT/RDY High
t8 0 ns min CS Falling Edge to SCLK Active Edge Setup Time4
t9 30 ns min Data Valid to SCLK Edge Setup Time
t10 25 ns min Data Valid to SCLK Edge Hold Time
t11 0 ns min CS Rising Edge to SCLK Edge Hold Time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
Rev. 0 | Page 5 of 20
ISINK (1.6mA WITH VDD = 5V,
100�A WITH VDD = 3V)
TO OUTPUT 1.6V
ISOURCE (200�A WITH VDD = 5V,
100�A WITH VDD = 3V)
Figure 2. Load Circuit for Timing Characterization
CS (I) t1 MSB t6
DOUT/RDY (O) t2 t3 t5
SCLK (I) LSB
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
SCLK (I) t9 LSB
DIN (I) t10
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS AD7791
Table 3. (TA= 25�C, unless otherwise noted.) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Parameter Rating rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
VDD to GND �0.3 V to +7 V of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
Analog Input Voltage to GND �0.3 V to VDD + 0.3 V device reliability.
Reference Input Voltage to GND �0.3 V to VDD + 0.3 V
Total AIN/REFIN Current (Indefinite) 30 mA
Digital Input Voltage to GND �0.3 V to VDD + 0.3 V
Digital Output Voltage to GND �0.3 V to VDD + 0.3 V
Operating Temperature Range �40�C to +105�C
Storage Temperature Range �65�C to +150�C
Maximum Junction Temperature 150�C
JA Thermal Impedance 206�C/W
JC Thermal Impedance 44�C/W
Lead Temperature, Soldering (10 sec) 300�C
IR Reflow, Peak Temperature 220�C
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK 1 10 DIN Pin
No. Mnemonic Function
CS 2 AD7791 9 DOUT/RDY
6 REFIN(�) Negative Reference Input. This reference
AIN(+) 3 TOP VIEW 8 VDD 7 GND input can lie anywhere between GND and
AIN(�) 4 (Not to Scale) 7 GND VDD � 0.1 V.
REF(+) 5 6 REF(�) Ground Reference Point.
Figure 5. Pin Configuration 8 VDD Supply Voltage, 2.5 V to 5.25 V.
Table 4. Pin Function Descriptions 9 DOUT/RDY Serial Data Output/Data Ready Output.
DOUT/RDY serves a dual purpose . It functions
Pin as a serial data output pin to access the out-
No. Mnemonic Function
put shift register of the ADC. The output shift
1 SCLK Serial Clock Input for Data Transfers to and register can contain data from any of the
from the ADC. The SCLK has a Schmitt-
triggered input, making the interface on-chip data or control registers. In addition,
suitable for opto-isolated applications. The
serial clock can be continuous with all data DOUT/RDY operates as a data ready pin,
transmitted in a continuous train of pulses.
Alternatively, it can be a noncontinuous going low to indicate the completion of a
clock with the information being trans-
mitted to or from the ADC in smaller conversion. If the data is not read after the
batches of data.
conversion, the pin will go high before the
next update occurs.
2 CS Chip Select Input. This is an active low logic The DOUT/RDY falling edge can be used as an
input used to select the ADC. CS can be interrupt to a processor, indicating that valid
data is available. With an external serial clock,
used to select the ADC in systems with the data can be read using the DOUT/RDY pin.
more than one device on the serial bus or as With CS low, the data/control word informa-
a frame synchronization signal in communi- tion is placed on the DOUT/RDY pin on the
cating with the device. CS can be hardwired SCLK falling edge and is valid on the SCLK
low, allowing the ADC to operate in 3-wire The end of a conversion is also indicated by
mode with SCLK, DIN, and DOUT used to the RDY bit in the status register. When CS is
interface with the device. high, the DOUT/RDY pin is three-stated but
the RDY bit remains active.
3 AIN(+) Analog Input. AIN(+) is the positive terminal 10 DIN Serial Data Input to the Input Shift Register
of the fully differential analog input. on the ADC. Data in this shift register is
transferred to the control registers within
4 AIN(�) Analog Input. AIN(�) is the negative termi- the ADC, the register selection bits of the
nal of the fully differential analog input. communications register identifying the
5 REFIN(+) Positive Reference Input. REFIN(+) can lie
anywhere between VDD and GND + 0.1 V.
The nominal reference voltage (REFIN(+) �
REFIN(�)) is 2.5 V, but the part functions
with a reference from 0.1 V to VDD.
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0 9 VDD = 3V
�20 8 VREF = 2.048V
�30 1.1875Hz UPDATE RATE
�50 TA = 25�C
�60 7 RMS NOISE = 1.25�F
�100 OCCURENCE 5
20 40 60 80 100 120 140 160 0 8388616
FREQUENCY (Hz) 04227-0-012 CODE
Figure 6. Frequency Response with 16.6 Hz Update Rate Figure 9. Noise Histogram for Clock Divide by 8 Mode
(CDIV0 = CDIV1 = 1)
VDD = 3V 8388616
100 VREF = 2.048V
9.5Hz UPDATE RATE
TA = 25�C
RMS NOISE = 1�V
OCCURENCE 60 CODE
VDD = 3V, VREF = 2.048V
1.1875Hz UPDATE RATE
0 TA = 25�C, RMS NOISE = 1.25�F
CODE 8388619 8388592 20 40 60 80 100
READ NO. 04227-0-013
Figure 7. Noise Distribution Histogram Figure 10. Noise Plot in Clock Divide by 8 Mode
(CDIV1 = CDIV0 = 0) (CDIV0 = CDIV1 = 1)
8388619 3.0 VDD = 5V
UPDATE RATE = 16.6Hz
TA = 25�C
RMS NOISE (�V) 2.0
VDD = 3V, VREF = 2.048V, 9.5Hz UPDATE RATE
8388591 TA = 25�C, RMS NOISE = 1�V
0 200 400 600 800 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
READ NO. 04227-0-011 VREF (V) 04227-0-015
Figure 8. Typical Noise Plot with 16.6 Hz Update Rate Figure 11. RMS Noise vs. Reference Voltage
(CDIV1 = CDIV0 = 0)
Rev. 0 | Page 9 of 20
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
RS1(0) RS0(0) R/W(0) CREAD(0) CH1(0) CH0(0)
Table 5. Communications Register Bit Designations
Bit Location Bit Name Description
CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6 0 This bit must be programmed to Logic 0 for correct operation.
CR5�CR4 RS1�RS0 Register Address Bits. These address bits are used to select which of the ADC's registers are being
selected during this serial interface communication. See Table 6.
CR3 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
CR1�CR0 CH1�CH0 These bits are used to select the analog input channel. The differential channel can be selected
(AIN(+)/AIN(�)) or an internal short (AIN(�)/AIN(�)) can be selected. Alternatively, the power supply can
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V � 5% on-chip reference as the reference source for the analog to
digital conversion. Any change in channel resets the filter and a new conversion is started.
Table 6. Register Selection Table 7. Channel Selection
RS1 RS0 Register Register Size CH1 CH0 Channel
0 0 Communications Register 0 0 AIN(+) � AIN(�)
during a Write Operation 8-Bit
0 1 Reserved
0 0 Status Register during a 8-Bit 1 0 AIN(�) � AIN(�)
Read Operation 24-Bit
1 1 VDD Monitor
0 1 Mode Register
1 0 Filter Register
1 1 Data Register
Rev. 0 | Page 10 of 20
STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1) ERR(0) 0(0) 0(0) 1(1) WL(1) CH1(0) CH0(0)
Table 8. Status Register Bit Designations
Bit Location Bit Name Description
SR7 RDY Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also set when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange. Cleared by a write operation to start a conversion.
SR5 0 This bit is automatically cleared.
SR4 0 This bit is automatically cleared.
SR3 1 This bit is automatically set.
SR2 1 This bit is automatically set if the device is an AD7791. It can be used to distinguish between the AD7791
and AD7790, in which the bit is cleared.
SR1�SR0 CH1�CH0 These bits indicate which channel is being converted by the ADC.
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit desig-
nations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes
the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup regis-
ter resets the modulator and filter and sets the RDY bit.
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
MD1(0) MD0(0) 0(0) 0(0) BO(0) U/B(0) BUF(1) 0(0)
Table 9. Mode Register Bit Designations
Bit Location Bit Name Description
MR7�MR6 MD1�MD0 Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. RDY goes low when a conversion is complete. The user can read these
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. In single
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up and performs a single conversion, which
occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active
(low) until the data is read or another conversion is performed. See Table 10.
MR5�MR4 0 This bit must be programmed with a Logic 0 for correct operation.
Rev. 0 | Page 11 of 20
Bit Location Bit Name Description
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal
MR2 U/B path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled
only when the buffer is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in
MR0 0 0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000,
zero differential input will result in an output code of 0x800000, and a positive full-scale differential
input will result in an output code of 0xFFFFFF.
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system.
This bit must be programmed with a Logic 0 for correct operation.
Table 10. Operating Modes
MD1 MD0 Mode
0 0 Continuous Conversion Mode
0 1 Reserved
1 0 Single Conversion Mode
1 1 Power-Down Mode
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word
rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the
filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0
0(0) 0(0) CDIV1(0) CDIV0(0) 0(0) FS2(1) FS1(0) FS0(0)
Table 11. Filter Register Bit Designations
Bit Location Bit Name Description
FR7�FR6 0 These bits must be programmed with a Logic 0 for correct operation.
FR5�FR4 CLKDIV1� These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and
CDIV0 the power is reduced. In the low power modes, the update rates will scale with the clock frequency so
that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00 Normal Mode
01 Clock Divided by 2
10 Clock Divided by 4
11 Clock Divided by 8
FR3 0 This bit must be programmed with a Logic 0 for correct operation.
FR2�FR0 FS2�FS0 These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and
the noise. See Table 12, which shows the allowable update rates when normal power mode is used. In
the low power modes, the update rate is scaled with the clock frequency. For example, if the internal
clock is divided by a factor of 2, the corresponding update rates will be divided by 2 also.
Rev. 0 | Page 12 of 20
Table 12. Update Rates
FS2 FS1 FS0 fADC (Hz) f3dB (Hz) RMS Noise (�V) Rejection
120 28 40 25 dB @ 60 Hz
0 0 0 100 24 25 25 dB @ 50 Hz
33.3 8 3.36
0 0 1 20 4.7 1.6 80 dB @ 60 Hz
16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting)
0 1 0 16.7 4 1.5 80 dB @ 50 Hz
13.3 3.2 1.2
0 1 1 9.5 2.3 1.1 67 dB @ 50/60 Hz
1 0 0
1 0 1
1 1 0
1 1 1
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
Rev. 0 | Page 13 of 20
ADC CIRCUIT INFORMATION numbers given are for the bipolar input range with a reference
of 2.5 V. These numbers are typical and generated with a
OVERVIEW differential input voltage of 0 V. The peak-to-peak resolution
figures represent the resolution for which there will be no code
The AD7791 is a low power ADC that incorporates a - flicker within a six-sigma limit. The output noise comes from
modulator, a buffer and on-chip digital filtering intended for the two sources. The first is the electrical noise in the semiconduc-
measurement of wide dynamic range, low frequency signals tor devices (device noise) used in the implementation of the
such as those in pressure transducers, weigh scales, and tem- modulator. The second is quantization noise, which is added
perature measurement applications. when the analog input is converted into the digital domain. The
device noise is at a low level and is independent of frequency.
The part has one differential input that can be buffered or The quantization noise starts at an even lower level but rises
unbuffered. Buffering the input channel means that the part can rapidly with increasing frequency to become the dominant
accommodate significant source impedances on the analog noise source.
input and that R, C filtering (for noise rejection or RFI reduc-
tion) can be placed on the analog input, if required. The device
requires an external reference of 2.5 nominal. Figure 12 shows
the basic connections required to operate the part.
Table 13. Typical Peak-to-Peak Resolution (Effective
POWER Resolution) vs. Update Rate
10�F Update Peak-toPeak Effective
0.1�F Rate Resolution Resolution
9.5 19.5 22
VDD 13.3 19 21.5
16.7 19 21.5
IN+ AD7791 16.6 19 21.5
OUT+ AIN(+) CS 20 18.5 21
IN� AIN(�) DOUT/RDY
MICROCONTROLLER 33.3 17.5 20
100 14.5 17
REFIN(�) 120 14 16.5
Figure 12. Basic Connection Diagram REDUCED CURRENT MODES
The output rate of the AD7791 (fADC) is user programmable The AD7791 has a current consumption of 160 �A maximum
with the settling time equal to 2 � tADC. Normal mode rejection when operated with a 5 V power supply, the buffer enabled, and
is the major function of the digital filter. Table 12 lists the avail- the clock operating at its maximum speed. The clock frequency
able output rates from the AD7791. Simultaneous 50 Hz and can be divided by a factor of 2, 4, or 8 before being applied to
60 Hz rejection is optimized when the update rate equals the modulator and filter, resulting in a reduction in the current
16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this consumption of the AD7791. Bits CDIV1 and CDIV0 in the
update rate (see Figure 6). filter register are used to enter these low power modes (see
When the internal clock is reduced, the update rate will also be
Table 13 shows the output rms noise, rms resolution, and peak- reduced. For example, if the filter bits are set to give an update
to-peak resolution (rounded to the nearest 0.5 LSB) for the rate of 16.6 Hz when the AD7791 is operated in full power
different update rates and input ranges for the AD7791. The mode, the update rate will equal 8.3 Hz in divide by 2 mode. In
the low power modes, there may be some degradation in the
Table 14. Low Power Mode Selection
CDIV[1:0] Clock Typ Current, Buffered (�A) Typ Current, Unbuffered (�A) 50 Hz/60 Hz Rejection (dB)
00 1 146 45 64
10 1/2 87 25 86
10 1/4 56
11 1/8 41
Rev. 0 | Page 14 of 20
DIGITAL INTERFACE AD7791
As previously outlined, the AD7791's programmable functions shift register while Figure 4 shows the timing for a write opera-
are controlled using a set of on-chip registers. Data is written to tion to the input shift register. In all modes except continuous
these registers via the part's serial interface and read access to read mode, it is possible to read the same word from the data
the on-chip registers is also provided by this interface. All com- register several times even though the DOUT/RDY line returns
munications with the part must start with a write to the high after the first read operation. However, care must be taken
communications register. After power-on or reset, the device to ensure that the read operations have been completed before
expects a write to its communications register. The data written the next output update occurs. In continuous read mode, the
to this register determines whether the next operation is a read data register can be read only once.
operation or a write operation and also determines to which
register this read or write operation occurs. Therefore, write The serial interface can operate in 3-wire mode by tying CS low.
access to any of the other registers on the part begins with a In this case, the SCLK, DIN, and DOUT/RDY lines are used to
write operation to the communications register followed by a communicate with the AD7791. The end of the conversion can
write to the selected register. A read operation from any other be monitored using the RDY bit in the status register. This
register (except when continuous read mode is selected) starts scheme is suitable for interfacing to microcontrollers. If CS is
with a write to the communications register followed by a read required as a decoding signal, it can be generated from a port
operation from the selected register. pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
The AD7791's serial interface consists of four signals: CS, DIN,
SCLK, and DOUT/RDY. The DIN line is used to transfer data The AD7791 can be operated with CS being used as a frame
into the on-chip registers while DOUT/RDY is used for access- synchronization signal. This scheme is useful for DSP interfaces.
ing from the on-chip registers. SCLK is the serial clock input for In this case, the first bit (MSB) is effectively clocked out by CS
the device and all data transfers (either on DIN or DOUT/RDY) since CS would normally occur after the falling edge of SCLK in
occur with respect to the SCLK signal. The DOUT/ RDY pin DSPs. The SCLK can continue to run between data transfers,
operates as a Data Ready signal also, the line going low when a provided the timing numbers are obeyed.
new data-word is available in the output register. It is reset high
when a read operation from the data register is complete. It also The serial interface can be reset by writing a series of 1s on the
goes high prior to the updating of the data register to indicate DIN input. If a Logic 1 is written to the AD7791 line for at least
when not to read from the device to ensure that a data read is 32 serial clock cycles, the serial interface is reset. This ensures
not attempted while the register is being updated. CS is used to that in 3-wire systems, the interface can be reset to a known
select a device. It can be used to decode the AD7791 in systems state if the interface gets lost due to a software error or some
where several components are connected to the serial bus. glitch in the system. Reset returns the interface to the state in
which it is expecting a write to the communications register.
Figure 3 and Figure 4 show timing diagrams for interfacing to This operation resets the contents of all registers to their power-
the AD7791 with CS being used to decode the part. Figure 3 on values.
shows the timing for a read operation from the AD7791's output
The AD7791 can be configured to continuously convert or to
CS perform a single conversion. See Figure 13 through Figure 15.
DIN 0x10 0x82 0x10 0x82
Figure 13. Single Conversion
Rev. 0 | Page 15 of 20
AD7791 Continuous Conversion Mode
Single Conversion Mode This is the default power-up mode. The AD7791 will continu-
ously convert, the RDY pin in the status register going low each
In single conversion mode, the AD7791 is placed in shutdown time a conversion is complete. If CS is low, the DOUT/RDY line
mode between conversions. When a single conversion is initi- will also go low when a conversion is complete. To read a con-
ated by setting MD1 to 1 and MD0 to 0 in the mode register, the version, the user can write to the communications register,
AD7791 powers up, performs a single conversion, and then indicating that the next operation is a read of the data register.
returns to shutdown mode. A conversion will require a time The digital conversion will be placed on the DOUT/RDY pin as
period of 2 � tADC. DOUT/RDY goes low to indicate the com- soon as SCLK pulses are applied to the ADC. DOUT/RDY will
pletion of a conversion. When the data-word has been read return high when the conversion is read. The user can read this
from the data register, DOUT/RDY will go high. If CS is low, register additional times, if required. However, the user must
DOUT/RDY will remain high until another conversion is initi- ensure that the data register is not being accessed at the comple-
ated and completed. The data register can be read several times, tion of the next conversion or else the new conversion word will
if required, even when DOUT/ RDY has gone high. be lost.
DIN DATA DATA
Figure 14. Continuous Conversion
Rev. 0 | Page 16 of 20
Continuous Read Mode AD7791
Rather than write to the communications register each time a before the next conversion is complete. If the user has not read
conversion is complete to access the data, the AD7791 can be the conversion before the completion of the next conversion or
placed in continuous read mode. By writing 001111XX to the if insufficient serial clocks are applied to the AD7791 to read the
communications register, the user needs only to apply the word, the serial output register is reset when the next conver-
appropriate number of SCLK cycles to the ADC and the 24-bit sion is complete and the new conversion is placed in the output
word will automatically be placed on the DOUT/RDY line serial register.
when a conversion is complete.
To exit the continuous read mode, the instruction 001110XX
When DOUT/RDY goes low to indicate the end of a conver- must be written to the communications register while the RDY
sion, sufficient SCLK cycles must be applied to the ADC and the pin is low. While in the continuous read mode, the ADC moni-
data conversion will be placed on the DOUT/RDY line. When tors activity on the DIN line so that it can receive the
the conversion is read, DOUT/RDY will return high until the instruction to exit the continuous read mode. Additionally, a
next conversion is available. In this mode, the data can be read reset will occur if 32 consecutive 1s are seen on DIN. Therefore,
only once. Also, the user must ensure that the data-word is read DIN should be held low in continuous read mode until an in-
struction is to be written to the device.
DATA DATA DATA
Figure 15. Continuous Read
Rev. 0 | Page 17 of 20
CIRCUIT DESCRIPTION If the ADC is configured for bipolar mode, the analog input
range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar
ANALOG INPUT CHANNEL option is chosen by programming the B/U bit in the mode
The AD7791 has one differential analog input channel. This is
connected to the on-chip buffer amplifier when the device is DATA OUTPUT CODING
operated in buffered mode and directly to the modulator when
the device is operated in unbuffered mode. In buffered mode When the ADC is configured for unipolar operation, the output
(the BUF bit in the mode register is set to 1), the input channel code is natural (straight) binary with a zero differential input
feeds into a high impedance input stage of the buffer amplifier. voltage resulting in a code of 00...00, a midscale voltage
Therefore, the input can tolerate significant source impedances resulting in a code of 100...000, and a full-scale input voltage
and is tailored for direct connection to external resistive-type resulting in a code of 111...111. The output code for any analog
sensors such as strain gauges or resistance temperature detec- input voltage can be represented as
Code = 2N � (AIN/VREF)
When BUF = 0, the part is operated in unbuffered mode. This
results in a higher analog input current. Note that this When the ADC is configured for bipolar operation, the output
unbuffered input path provides a dynamic load to the driving code is offset binary with a negative full-scale voltage resulting
source. Therefore, resistor/capacitor combinations on the input in a code of 000...000, a zero differential input voltage resulting
pins can cause dc gain errors, depending on the output in a code of 100...000, and a positive full-scale input voltage
impedance of the source that is driving the ADC input. Table 15 resulting in a code of 111...111. The output code for any analog
shows the allowable external resistance/capacitance values for input voltage can be represented as
unbuffered mode such that no gain error at the 20-bit level is
introduced. Code = 2N � 1 � [(AIN/VREF) + 1]
Table 15. External R-C Combination for No 20-Bit Gain Error where AIN is the analog input voltage and N = 24.
C (pF) R () REFERENCE INPUT
50 16.7K The AD7791 has a fully differential input capability for the
channel. The common-mode range for these differential inputs
100 9.6K is from GND to VDD. The reference input is unbuffered and,
therefore, excessive R-C source impedances will introduce gain
500 2.2K errors. The reference voltage REFIN (REFIN(+) � REFIN(�)) is
2.5 V nominal, but the AD7791 is functional with reference
1000 1.1K voltages from 0.1 V to VDD. In applications where the excitation
(voltage or current) for the transducer on the analog input also
5000 160 drives the reference voltage for the part, the effect of the low
frequency noise in the excitation source will be removed
The absolute input voltage range in buffered mode is restricted because the application is ratiometric. If the AD7791 is used
to a range between GND + 100 mV and VDD � 100 mV. Care in a nonratiometric application, a low noise reference should
must be taken in setting up the common-mode voltage so that be used.
these limits are not exceeded. Otherwise, there will be degrada-
tion in linearity and noise performance. Recommended 2.5 V reference voltage sources for the AD7791
include the ADR381 and ADR391, which are low noise, low
The absolute input voltage in unbuffered mode includes the power references. In a system that operates from a 2.5 V power
range between GND � 30 mV and VDD + 30 mV as a result of supply, the reference voltage source will require some head-
being unbuffered. The negative absolute input voltage limit does room. In this case, a 2.048 V reference such as the ADR380 or
allow the possibility of monitoring small true bipolar signals ADR390 can be used, requiring only 300 mV of headroom. Also
with respect to GND. note that the reference inputs provide a high impedance,
dynamic load. Because the input impedance of each reference
BIPOLAR/UNIPOLAR CONFIGURATION input is dynamic, resistor/ capacitor combinations on these
inputs can cause dc gain errors, depending on the output
The analog input to the AD7791 can accept either unipolar or impedance of the source that is driving the reference inputs.
bipolar input voltage ranges. A bipolar input range does not
imply that the part can tolerate negative voltages with respect to
system GND. Unipolar and bipolar signals on the AIN(+) input
are referenced to the voltage on the AIN(�) input. For example,
if AIN(�) is 2.5 V and the ADC is configured for unipolar
mode, the input voltage range on the AIN(+) pin is 2.5 V to 5 V.
Rev. 0 | Page 18 of 20
Reference voltage sources like those recommended above AD7791
(e.g., ADR391) will typically have low output impedances and
are, therefore, tolerant to having decoupling capacitors on The printed circuit board that houses the AD7791 should be
REFIN(+) without introducing gain errors in the system. designed such that the analog and digital sections are separated
Deriving the reference input voltage across an external resistor and confined to certain areas of the board. A minimum etch
will mean that the reference input sees a significant external technique is generally best for ground planes because it gives
source impedance. External decoupling on the REFIN pins the best shielding.
would not be recommended in this type of circuit
configuration. It is recommended that the AD7791's GND pin be tied to the
AGND plane of the system. In any layout, it is important that
VDD MONITOR the user keep in mind the flow of currents in the system, ensur-
ing that the return paths for all currents are as close as possible
Along with converting external voltages, the analog input chan- to the paths the currents took to reach their destinations. Avoid
nel can be used to monitor the voltage on the VDD pin. When the forcing digital currents to flow through the AGND sections of
CH1 and CH0 bits in the communications register are set to 1, the layout.
the voltage on the VDD pin is internally attenuated by 5 and the
resultant voltage is applied to the - modulator using an inter- The AD7791's ground plane should be allowed to run under the
nal 1.17 V reference for analog to digital conversion. This is AD7791 to prevent noise coupling. The power supply lines to
useful because variations in the power supply voltage can be the AD7791 should use as wide a trace as possible to provide
monitored. low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching signals such as clocks should
GROUNDING AND LAYOUT be shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
Since the analog inputs and reference inputs of the ADC are near the analog inputs. Avoid crossover of digital and analog
differential, most of the voltages in the analog modulator are signals. Traces on opposite sides of the board should run at
common-mode voltages. The excellent common-mode rejec- right angles to each other. This will reduce the effects of
tion of the part will remove common-mode noise on these feedthrough through the board. A microstrip technique is by far
inputs. The digital filter will provide rejection of broadband the best, but it is not always possible with a double-sided board.
noise on the power supply, except at integer multiples of the In this technique, the component side of the board is dedicated
modulator sampling frequency. The digital filter also removes to ground planes, while signals are placed on the solder side.
noise from the analog and reference inputs, provided that these
noise sources do not saturate the analog modulator. As a result, Good decoupling is important when using high resolution
the AD7791 is more immune to noise interference than a con- ADCs. VDD should be decoupled with 10 �F tantalum in parallel
ventional high resolution converter. However, because the with 0.1 �F capacitors to GND. To achieve the best from these
resolution of the AD7791 is so high, and the noise levels from decoupling components, they should be placed as close as
the AD7791 are so low, care must be taken with regard to possible to the device, ideally right up against the device. All
grounding and layout. logic chips should be decoupled with 0.1 �F ceramic capacitors
Rev. 0 | Page 19 of 20
3.00 BSC 4.90 BSC
0.85 1.10 MAX
0.15 0.27 SEATING 0.23 8� 0.60
PLANE 0.08 0� 0.40
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 16. 10-Lead Mini Small Outline Package [MSOP]
Dimensions shown in millimeters
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Table 16. Ordering Guide
Model Temperature Range Package Description Package Option Branding
10-Lead Mini Small Outline Package (MSOP) RM-10 COT
AD7791BRM �40�C to +105�C 10-Lead Mini Small Outline Package (MSOP) RM-10 COT
AD7791BRM-REEL �40�C to +105�C
� 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective companies.
Rev. 0 | Page 20 of 20
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